Multistage Interconnection Network Reliability

the input transitions at t = t 1 and t = f Z imply a pulse at the input port Il of the component. The mechanism is illustrated through an example presented subsequently. ns and the input signals at ports A and B. Although both of the input signals at A and B are logical 1 and 2 ns in width that is much larger than t p / h = 0.5 ns, the overlapping region where both inputs are high constitutes a pulse width of only (2-1.95) ns = 0.05 ns that is much smaller than tplh = 0.5 ns and, consequently, may not switch the AND gate. The mechanism presented earlier in this section identifies this situation and discards the effects of the input transitions at t = 1.95 ns and t = 2 ns as discussed subsequently. Corresponding to the transition at port A at t = 0, an output value 0 is determined by evaluating the AND gate description under the assumption that fph/ = t p / h = 0 ns and this does not indicate a change from the previous value of the AND gate, the data structure continues to store the previous information. Corresponding to the second transition at port B at t = 1.95 ns, an output value 1 is determined similar to the previous instance and stored in the data structure along with t = 1.95 ns and the input port B. Corresponding to the third transition at A at t = 2 ns, an output value 0 is determined. Since a pulse of value 1 is implied at the output caused by the input transitions at t = 1.95 ns and t = 2 ns and the difference (2-1.95) = 0.05 ns is smaller than t p / h = 0.5 ns, the resulting effect of the combination of input transitions at t = 1.95 ns and t=2 ns is discarded. Consequently, the mechanism correctly predicts no change in the value at the output port. The limitations of the preemptive scheduling mechanism may be expressed as follows. The semantics of behavior descriptions of components depends to a significant extent on the timed assignment statements. When a number of preemptions occur among multiple events, it may be difficult to understand the behavior of a component from its description. Also, where the behavior of a component in a digital design is such …